The present invention relates to radio receiver for FSK signals, such a receiver may be used as a paging receiver.
British Patent Specification 2,143,386A discloses a radio receiver suitable for use with FSK or angle modulated signals. The radio receiver comprises a frequency down-conversion stage which utilizes direct conversion techniques to provide zero IF quadrature baseband signals I and Q. The I and Q signals are limited in respective limiting amplifiers to form corresponding I and Q square wave signals. Pulse forming networks, for example differentiators, are coupled to the outputs of the respective limiting amplifiers to derive respective first and second pulse sequences, the outputs of which represent the polarity changes in the corresponding I and Q square wave signals. First and second multipliers are provided in which the I and Q square wave signals are multiplied by the second and first pulse sequences, respectively, to produce two pulse trains. Means are provided for combining the two pulse trains to give a digital output signal the frequency of which is equal to the sum of the frequencies of the two pulse trains. The digital output signal is applied to a low pass filter which produces a simulation of the original baseband modulation. More particularly the pulses in the digital output signal are smoothed to give approximately a dc level, the magnitude of which depends on the pulse frequency which in turn depends on the frequency of the beat note, that is the frequency difference between the receiver's local oscillator frequency and the frequency of the modulated signal.
The described receiver in principle functions satisfactorily if there is no drift between the local oscillator and modulated signal frequencies. However, in a practical situation drift will occur and the effect will be that the beat frequencies corresponding to binary "1" and "0" will be different. As a consequence of the low pass filtering the magnitude of the dc level will vary in accordance with the drift. In order to detect the value of the modulated signal a dynamic bit slicer is required. Dynamic bit slicers are complicated to design and consume a relative large current which undesirably increases the battery drain. The turn-on time of the receiver is lengthened by the use of the dynamic bit slicer which is a disadvantage when the receiver is operating in a battery economizing regime.
A reason for using a zero IF receiver is that it can be largely fabricated as an integrated circuit. However, as is well known, reactive components such as capacitors are expensive to integrate and if possible are avoided. Using a low pass filter to obtain an output dc signal mitigates against this as it requires one or more capacitors.